Datasheet

SD16_A Operation

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26.2.11.2 Interrupt Delay Operation

The SD16INTDLYx bits control the timing for the first interrupt service request for the corresponding

channel. This feature delays the interrupt request for a completed conversion by up to four conversion

cycles allowing the digital filter to settle prior to generating an interrupt request. The delay is applied each

time the SD16SC bit is set or when the SD16GAINx or SD16INCHx bits for the channel are modified.

SD16INTDLYx disables overflow interrupt generation for the channel for the selected number of delay

cycles. Interrupt requests for the delayed conversions are not generated during the delay.

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SD16_A SLAU144J–December 2004–Revised July 2013

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