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3.4.4.4 Format-I (Double Operand) Instruction Cycles and Lengths
Table 3-16 lists the length and CPU cycles for all addressing modes of format-I instructions.
Table 3-16. Format 1 Instruction Cycles and Lengths
Addressing Mode
Length of
Src Dst No. of Cycles Instruction Example
Rn Rm 1 1
MOV R5,R8
PC 2 1
BR R9
x(Rm) 4 2
ADD R5,4(R6)
EDE 4 2
XOR R8,EDE
&EDE 4 2
MOV R5,&EDE
@Rn Rm 2 1
AND @R4,R5
PC 2 1
BR @R8
x(Rm) 5 2
XOR @R5,8(R6)
EDE 5 2
MOV @R5,EDE
&EDE 5 2
XOR @R5,&EDE
@Rn+ Rm 2 1
ADD @R5+,R6
PC 3 1
BR @R9+
x(Rm) 5 2
XOR @R5,8(R6)
EDE 5 2
MOV @R9+,EDE
&EDE 5 2
MOV @R9+,&EDE
#N Rm 2 2
MOV #20,R9
PC 3 2
BR #2AEh
x(Rm) 5 3
MOV #0300h,0(SP)
EDE 5 3
ADD #33,EDE
&EDE 5 3
ADD #33,&EDE
x(Rn) Rm 3 2
MOV 2(R5),R7
PC 3 2
BR 2(R6)
TONI 6 3
MOV 4(R7),TONI
x(Rm) 6 3
ADD 4(R4),6(R9)
&TONI 6 3
MOV 2(R4),&TONI
EDE Rm 3 2
AND EDE,R6
PC 3 2
BR EDE
TONI 6 3
CMP EDE,TONI
x(Rm) 6 3
MOV EDE,0(SP)
&TONI 6 3
MOV EDE,&TONI
&EDE Rm 3 2
MOV &EDE,R8
PC 3 2
BRA &EDE
TONI 6 3
MOV &EDE,TONI
x(Rm) 6 3
MOV &EDE,0(SP)
&TONI 6 3
MOV &EDE,&TONI
61
SLAU144J–December 2004–Revised July 2013 CPU
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