Datasheet

Input
Voltage
SD16MEMx
−V
FSR
+V
FSR
7FFFh
8000h
Bipolar Output: 2’s complement
Input
Voltage
SD16MEMx
−V
FSR
+V
FSR
FFFFh
8000h
Bipolar Output: Offset Binary
0000h
0000h
Input
Voltage
SD16MEMx
−V
FSR
+V
FSR
FFFFh
Unipolar Output
0000h
www.ti.com SD16_A Operation
26.2.8 Conversion Memory Register: SD16MEM0
The SD16MEM0 register is associated with the SD16_A channel. Conversion results are moved to the
SD16MEM0 register with each decimation step of the digital filter. The SD16IFG bit is set when new data
is written to SD16MEM0. SD16IFG is automatically cleared when SD16MEM0 is read by the CPU or may
be cleared with software.
26.2.8.1 Output Data Format
The output data format is configurable in two's complement, offset binary or unipolar mode as shown in
Table 26-3. The data format is selected by the SD16DF and SD16UNI bits.
Table 26-3. Data Format
Digital Filter Output
SD16UNI SD16DF Format Analog Input SD16MEM0
(1)
(OSR = 256)
+FSR FFFF FFFFFF
0 0 Bipolar Offset Binary ZERO 8000 800000
-FSR 0000 000000
+FSR 7FFF 7FFFFF
0 1 Bipolar Twos Compliment ZERO 0000 000000
-FSR 8000 800000
+FSR FFFF FFFFFF
1 0 Unipolar ZERO 0000 800000
-FSR 0000 000000
(1)
Independent of SD16OSRx and SD16XOSR settings; SD16LSBACC = 0.
NOTE: Offset Measurements and Data Format
Any offset measurement done either externally or using the internal differential pair A7 would
be appropriate only when the channel is operating under bipolar mode with SD16UNI = 0.
Figure 26-6 shows the relationship between the full-scale input voltage range from -V
FSR
to +V
FSR
and the
conversion result. The data formats are illustrated.
Figure 26-6. Input Voltage vs Digital Output
607
SLAU144J–December 2004–Revised July 2013 SD16_A
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