Datasheet

−140
−120
−100
−80
−60
−40
−20
0
Frequency
GAIN [dB]
f
S
f
M
3 3
M M
M M
f f
sinc OSR × × sin OSR × ×
f f
1
H(f) = = ×
OSR
f f
sinc × sin ×
f f
p p
p p
é ù é ù
æ ö æ ö
ê ú ê ú
ç ÷ ç ÷
ç ÷ ç ÷
ê ú ê ú
è ø è ø
ê ú ê ú
æ ö æ ö
ê ú ê ú
ç ÷ ç ÷
ç ÷ ç ÷
ê ú ê ú
è ø è ø
ë û ë û
3
-OSR
-1
1 1 – z
H(z) = ×
OSR
1 – z
æ ö
ç ÷
ç ÷
è ø
www.ti.com SD16_A Operation
Table 26-2. Sampling Capacitance
PGA Gain Sampling Capacitance, C
S
1 1.25 pF
2, 4 2.5 pF
8 5 pF
16, 32 10 pF
26.2.7 Digital Filter
The digital filter processes the 1-bit data stream from the modulator using a SINC
3
comb filter. The
transfer function is described in the z-Domain by:
and in the frequency domain by:
where the oversampling rate, OSR, is the ratio of the modulator frequency f
M
to the sample frequency f
S
.
Figure 26-3 shows the filter's frequency response for an OSR of 32. The first filter notch is at f
S
= f
M
/OSR.
The notch's frequency can be adjusted by changing the modulator's frequency, f
M
, using SD16SSELx and
SD16DIVx and the oversampling rate using the SD16OSRx and SD16XOSR bits.
The digital filter for each enabled ADC channel completes the decimation of the digital bit-stream and
outputs new conversion results to the SD16MEM0 register at the sample frequency f
S
.
Figure 26-3. Comb Filter Frequency Response With OSR = 32
Figure 26-4 shows the digital filter step response and conversion points. For step changes at the input
after start of conversion a settling time must be allowed before a valid conversion result is available. The
SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input. If the
step occurs synchronously to the decimation of the digital filter the valid data will be available on the third
conversion. An asynchronous step will require one additional conversion before valid data is available.
603
SLAU144J–December 2004–Revised July 2013 SD16_A
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