Datasheet

CC CC
S Ax S+ S–
Settling
AV AV
1
f = and V = max – V , – V
2 × t 2 2
æ ö
ç ÷
ç ÷
è ø
17
Ax
Settling S S
REF
GAIN × 2 × V
t (R + 1 k ) × C × ln
V
æ ö
ç ÷
³ W
ç ÷
è ø
R
S
1 k
V
S+
MSP430
C
S
V
S+
= Positive external source voltage
V
S−
= Negative external source voltage
R
S
= External source resistance
C
S
= Sampling capacitance
R
S
1 k
V
S−
C
S
AV
CC
/ 2
† Not implemented in MSP430x20x3 devices
†
†
SD16_A Operation www.ti.com
During conversion any modification to the SD16INCHx and SD16GAINx bits will become effective with the
next decimation step of the digital filter. After these bits are modified, the next three conversions may be
invalid due to the settling time of the digital filter. This can be handled automatically with the
SD16INTDLYx bits. When SD16INTDLY = 00h, conversion interrupt requests will not begin until the fourth
conversion after a start condition.
On devices implementing the high impedance input buffer it can be enabled using the SD16BUFx bits.
The speed settings are selected based on the SD16_A modulator frequency as shown in Table 26-1.
Table 26-1. High Input Impedance Buffer
SD16BUFx Buffer SD16 Modulator Frequency f
M
00 Buffer disabled
01 Low speed/current f
M
< 200 kHz
10 Medium speed/current 200 kHz < f
M
< 700 kHz
11 High speed/current 700 kHz < f
M
< 1.1 MHz
An external RC anti-aliasing filter is recommended for the SD16_A to prevent aliasing of the input signal.
The cutoff frequency should be < 10 kHz for a 1-MHz modulator clock and OSR = 256. The cutoff
frequency may set to a lower frequency for applications that have lower bandwidth requirements.
26.2.6 Analog Input Characteristics
The SD16_A uses a switched-capacitor input stage that appears as an impedance to external circuitry as
shown in Figure 26-2.
Figure 26-2. Analog Input Equivalent Circuit
When the buffers are used, R
S
does not affect the sampling frequency f
S
. However, when the buffers are
not used or are not present on the device, the maximum sampling frequency f
S
may be calculated from the
minimum settling time t
Settling
of the sampling circuit given by:
where
with V
S+
and V
S-
referenced to AV
SS
.
C
S
varies with the gain setting as shown in Table 26-2.
602
SD16_A SLAU144J–December 2004–Revised July 2013
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