Datasheet

www.ti.com
13.2.6 Timer_B Interrupts ............................................................................................. 388
13.3 Timer_B Registers ....................................................................................................... 390
13.3.1 Timer_B Control Register TBCTL ........................................................................... 391
13.3.2 TBR, Timer_B Register ....................................................................................... 392
13.3.3 TBCCRx, Timer_B Capture/Compare Register x .......................................................... 392
13.3.4 TBCCTLx, Capture/Compare Control Register ............................................................ 393
13.3.5 TBIV, Timer_B Interrupt Vector Register ................................................................... 394
14 Universal Serial Interface (USI) .......................................................................................... 395
14.1 USI Introduction .......................................................................................................... 396
14.2 USI Operation ............................................................................................................ 399
14.2.1 USI Initialization ................................................................................................ 399
14.2.2 USI Clock Generation ......................................................................................... 399
14.2.3 SPI Mode ....................................................................................................... 400
14.2.4 I
2
C Mode ........................................................................................................ 402
14.3 USI Registers ............................................................................................................. 405
14.3.1 USICTL0, USI Control Register 0 ............................................................................ 406
14.3.2 USICTL1, USI Control Register 1 ............................................................................ 407
14.3.3 USICKCTL, USI Clock Control Register .................................................................... 408
14.3.4 USICNT, USI Bit Counter Register .......................................................................... 408
14.3.5 USISRL, USI Low Byte Shift Register ....................................................................... 409
14.3.6 USISRH, USI High Byte Shift Register ...................................................................... 409
15 Universal Serial Communication Interface, UART Mode ........................................................ 410
15.1 USCI Overview ........................................................................................................... 411
15.2 USCI Introduction: UART Mode ........................................................................................ 411
15.3 USCI Operation: UART Mode .......................................................................................... 413
15.3.1 USCI Initialization and Reset ................................................................................. 413
15.3.2 Character Format .............................................................................................. 413
15.3.3 Asynchronous Communication Formats .................................................................... 413
15.3.4 Automatic Baud Rate Detection .............................................................................. 416
15.3.5 IrDA Encoding and Decoding ................................................................................ 417
15.3.6 Automatic Error Detection .................................................................................... 418
15.3.7 USCI Receive Enable ......................................................................................... 418
15.3.8 USCI Transmit Enable ........................................................................................ 419
15.3.9 UART Baud Rate Generation ................................................................................ 419
15.3.10 Setting a Baud Rate .......................................................................................... 421
15.3.11 Transmit Bit Timing ........................................................................................... 422
15.3.12 Receive Bit Timing ........................................................................................... 422
15.3.13 Typical Baud Rates and Errors ............................................................................. 424
15.3.14 Using the USCI Module in UART Mode with Low Power Modes ...................................... 426
15.3.15 USCI Interrupts ............................................................................................... 426
15.4 USCI Registers: UART Mode .......................................................................................... 428
15.4.1 UCAxCTL0, USCI_Ax Control Register 0 .................................................................. 429
15.4.2 UCAxCTL1, USCI_Ax Control Register 1 .................................................................. 430
15.4.3 UCAxBR0, USCI_Ax Baud Rate Control Register 0 ...................................................... 430
15.4.4 UCAxBR1, USCI_Ax Baud Rate Control Register 1 ...................................................... 430
15.4.5 UCAxMCTL, USCI_Ax Modulation Control Register ...................................................... 431
15.4.6 UCAxSTAT, USCI_Ax Status Register ..................................................................... 431
15.4.7 UCAxRXBUF, USCI_Ax Receive Buffer Register ......................................................... 432
15.4.8 UCAxTXBUF, USCI_Ax Transmit Buffer Register ......................................................... 432
15.4.9 UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register ................................................ 432
15.4.10 UCAxIRRCTL, USCI_Ax IrDA Receive Control Register ............................................... 432
15.4.11 UCAxABCTL, USCI_Ax Auto Baud Rate Control Register ............................................. 433
15.4.12 IE2, Interrupt Enable Register 2 ............................................................................ 433
6
Contents SLAU144J–December 2004–Revised July 2013
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated