Datasheet

www.ti.com

DAC12 Registers

DAC12IFG Bit 2 DAC12 Interrupt flag

0 No interrupt pending

1 Interrupt pending

DAC12ENC Bit 1 DAC12 enable conversion. This bit enables the DAC12 module when DAC12LSELx > 0. when

DAC12LSELx = 0, DAC12ENC is ignored.

0 DAC12 disabled

1 DAC12 enabled

DAC12GRP Bit 0 DAC12 group. Groups DAC12_x with the next higher DAC12_x. Not used for DAC12_1.

0 Not grouped

1 Grouped

25.3.2 DAC12_xDAT, DAC12 Data Register

15 14 13 12 11 10 9 8

0 0 0 0 DAC12 Data

r(0) r(0) r(0) r(0) rw-(0) rw-(0) rw-(0) rw-(0)

7 6 5 4 3 2 1 0

DAC12 Data

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

Unused Bits 15-12 Unused. These bits are always 0 and do not affect the DAC12 core.

DAC12 Data Bits 11-0 DAC12 data

DAC12 Data Format DAC12 Data

12-bit binary The DAC12 data are right-justified. Bit 11 is the MSB.

12-bit 2s complement The DAC12 data are right-justified. Bit 11 is the MSB (sign).

8-bit binary The DAC12 data are right-justified. Bit 7 is the MSB. Bits 11-8 are don’t care and do not affect the DAC12 core.

8-bit 2s complement The DAC12 data are right-justified. Bit 7 is the MSB (sign). Bits 11-8 are don’t care and do not affect the

DAC12 core.

597

SLAU144J–December 2004–Revised July 2013 DAC12

Submit Documentation Feedback