Datasheet
DAC12 Registers
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25.3.1 DAC12_xCTL, DAC12 Control Register
15 14 13 12 11 10 9 8
DAC12OPS DAC12SREFx DAC12RES DAC12LSELx DAC12CALON DAC12IR
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
7 6 5 4 3 2 1 0
DAC12AMPx DAC12DF DAC12IE DAC12IFG DAC12ENC DAC12GRP
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Can be modified only when DAC12ENC = 0
DAC12OPS Bit 15 DAC12 output select
0 DAC12_0 output on P6.6, DAC12_1 output on P6.7
1 DAC12_0 output on V
eREF+
, DAC12_1 output on P6.5
DAC12SREFx Bits 14-13 DAC12 select reference voltage
00 V
REF+
01 V
REF+
10 V
eREF+
11 V
eREF+
DAC12RES Bit 12 DAC12 resolution select
0 12-bit resolution
1 8-bit resolution
DAC12LSELx Bits 11-10 DAC12 load select. Selects the load trigger for the DAC12 latch. DAC12ENC must be set for the DAC to
update, except when DAC12LSELx = 0.
00 DAC12 latch loads when DAC12_xDAT written (DAC12ENC is ignored)
01 DAC12 latch loads when DAC12_xDAT written, or, when grouped, when all DAC12_xDAT registers
in the group have been written.
10 Rising edge of Timer_A.OUT1 (TA1)
11 Rising edge of Timer_B.OUT2 (TB2)
DAC12CALON Bit 9 DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence and is automatically reset
when the calibration completes.
0 Calibration is not active
1 Initiate calibration/calibration in progress
DAC12IR Bit 8 DAC12 input range. This bit sets the reference input and voltage output range.
0 DAC12 full-scale output = 3x reference voltage
1 DAC12 full-scale output = 1x reference voltage
DAC12AMPx Bits 7-5 DAC12 amplifier setting. These bits select settling time vs current consumption for the DAC12 input and
output amplifiers.
DAC12AMPx Input Buffer Output Buffer
000 Off DAC12 off, output high Z
001 Off DAC12 off, output 0 V
010 Low speed/current Low speed/current
011 Low speed/current Medium speed/current
100 Low speed/current High speed/current
101 Medium speed/current Medium speed/current
110 Medium speed/current High speed/current
111 High speed/current High speed/current
DAC12DF Bit 4 DAC12 data format
0 Straight binary
1 2s complement
DAC12IE Bit 3 DAC12 interrupt enable
0 Disabled
1 Enabled
596
DAC12 SLAU144J–December 2004–Revised July 2013
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