Datasheet

DAC12_0
DAC12GRP
DAC12_0
DAC12ENC
TimerA_OUT1
DAC12_0
Latch Trigger
DAC12_0 Updated
DAC12_0 DAC12LSELx = 2 DAC12_0 DAC12LSELx > 0AND
DAC12_1 DAC12LSELx = 2
DAC12_0DAT
New Data
DAC12_1DAT
New Data
DAC12_0 and DAC12_1
Updated Simultaneously
DAC12 Operation www.ti.com
Figure 25-6. DAC12 Group Update Example, Timer_A3 Trigger
NOTE: DAC12 Settling Time
The DMA controller is capable of transferring data to the DAC12 faster than the DAC12
output can settle. The user must assure the DAC12 settling time is not violated when using
the DMA controller. See the device-specific data sheet for parameters.
25.2.7 DAC12 Interrupts
The DAC12 interrupt vector is shared with the DMA controller on some devices (see device-specific data
sheet for interrupt assignment). In this case, software must check the DAC12IFG and DMAIFG flags to
determine the source of the interrupt.
The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched from the DAC12_xDAT
register into the data latch. When DAC12LSELx = 0, the DAC12IFG flag is not set.
A set DAC12IFG bit indicates that the DAC12 is ready for new data. If both the DAC12IE and GIE bits are
set, the DAC12IFG generates an interrupt request. The DAC12IFG flag is not reset automatically. It must
be reset by software.
594
DAC12 SLAU144J–December 2004–Revised July 2013
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