Datasheet

Output Voltage

DAC Data

Full-Scale Code

Output Voltage

DAC Data

Negative Offset

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DAC12 Operation

Figure 25-4. Negative Offset

When the output amplifier has a positive offset, a digital input of zero does not result in a zero output

voltage. The DAC12 output voltage reaches the maximum output level before the DAC12 data reaches

the maximum code. This is shown in Figure 25-5.

Figure 25-5. Positive Offset

The DAC12 has the capability to calibrate the offset voltage of the output amplifier. Setting the

DAC12CALON bit initiates the offset calibration. The calibration should complete before using the DAC12.

When the calibration is complete, the DAC12CALON bit is automatically reset. The DAC12AMPx bits

should be configured before calibration. For best calibration results, port and CPU activity should be

minimized during calibration.

25.2.6 Grouping Multiple DAC12 Modules

Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each

DAC12 output. Hardware ensures that all DAC12 modules in a group update simultaneously independent

of any interrupt or NMI event.

DAC12_0 and DAC12_1 are grouped by setting the DAC12GRP bit of DAC12_0. The DAC12GRP bit of

DAC12_1 is don’t care. When DAC12_0 and DAC12_1 are grouped:

• The DAC12_1 DAC12LSELx bits select the update trigger for both DACs

• The DAC12LSELx bits for both DACs must be > 0

• The DAC12ENC bits of both DACs must be set to 1

When DAC12_0 and DAC12_1 are grouped, both DAC12_xDAT registers must be written to before the

outputs update, even if data for one or both of the DACs is not changed. Figure 25-6 shows a latch-update

timing example for grouped DAC12_0 and DAC12_1.

When DAC12_0 DAC12GRP = 1 and both DAC12_x DAC12LSELx > 0 and either DAC12ENC = 0,

neither DAC12 updates.

593

SLAU144J–December 2004–Revised July 2013 DAC12

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