Datasheet

OUT REF
DAC12_xDAT
V = V ×
256
OUT REF
DAC12_xDAT
V = V × 3 ×
256
OUT REF
DAC12_xDAT
V = V ×
4096
OUT REF
DAC12_xDAT
V = V × 3 ×
4096
www.ti.com DAC12 Operation
25.2 DAC12 Operation
The DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed
in the following sections.
25.2.1 DAC12 Core
The DAC12 can be configured to operate in 8-bit or 12-bit mode using the DAC12RES bit. The full-scale
output is programmable to be 1x or 3x the selected reference voltage via the DAC12IR bit. This feature
allows the user to control the dynamic range of the DAC12. The DAC12DF bit allows the user to select
between straight binary data and 2s-compliment data for the DAC. When using straight binary data format,
the formula for the output voltage is given in Table 25-1.
Table 25-1. DAC12 Full-Scale Range (V
REF
= V
eREF+
or V
REF+
)
Resolution DAC12RES DAC12IR Output Voltage Formula
12 bit 0 0
12 bit 0 1
8 bit 1 0
8 bit 1 1
In 8-bit mode, the maximum useable value for DAC12_xDAT is 0FFh. In 12-bit mode, the maximum
useable value for DAC12_xDAT is 0FFFh. Values greater than these may be written to the register, but all
leading bits are ignored.
25.2.1.1 DAC12 Port Selection
The DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog inputs, and also the V
eREF+
pins. When DAC12AMPx > 0, the DAC12 function is automatically selected for the pin, regardless of the
state of the associated PxSELx and PxDIRx bits. The DAC12OPS bit selects between the P6 pins and the
V
eREF+
pins for the DAC outputs. For example, when DAC12OPS = 0, DAC12_0 outputs on P6.6 and
DAC12_1 outputs on P6.7. When DAC12OPS = 1, DAC12_0 outputs on V
eREF+
and DAC12_1 outputs on
P6.5. See the port pin schematic in the device-specific data sheet for more details.
25.2.2 DAC12 Reference
The reference for the DAC12 is configured to use either an external reference voltage or the internal 1.5-
V/2.5-V reference from the ADC12 module with the DAC12SREFx bits. When DAC12SREFx = {0,1} the
V
REF+
signal is used as the reference and when DAC12SREFx = {2,3} the V
eREF+
signal is used as the
reference.
To use the ADC12 internal reference, it must be enabled and configured via the applicable ADC12 control
bits.
25.2.2.1 DAC12 Reference Input and Voltage Output Buffers
The reference input and voltage output buffers of the DAC12 can be configured for optimized settling time
vs power consumption. Eight combinations are selected using the DAC12AMPx bits. In the low/low
setting, the settling time is the slowest, and the current consumption of both buffers is the lowest. The
medium and high settings have faster settling times, but the current consumption increases. See the
device-specific data sheet for parameters.
25.2.3 Updating the DAC12 Voltage Output
The DAC12_xDAT register can be connected directly to the DAC12 core or double buffered. The trigger
for updating the DAC12 voltage output is selected with the DAC12LSELx bits.
591
SLAU144J–December 2004–Revised July 2013 DAC12
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