Datasheet

Instruction Set

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3.4.2 Single-Operand (Format II) Instructions

Figure 3-10 illustrates the single-operand instruction format.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code B/W Ad D/S-Reg

Figure 3-10. Single Operand Instruction Format

Table 3-12 lists and describes the single operand instructions.

Table 3-12. Single Operand Instructions

Status Bits

S-Reg,

Mnemonic Operation

D-Reg

V N Z C

C → MSB →.......LSB → C * * * *

RRC(.B) dst

MSB → MSB →....LSB → C 0 * * *

RRA(.B) dst

SP – 2 → SP, src → @SP - - - -

PUSH(.B) src

Swap bytes - - - -

SWPB dst

SP – 2 → SP, PC+2 → @SP - - - -

CALL dst

dst → PC

TOS → SR, SP + 2 → SP * * * *

RETI

TOS → PC,SP + 2 → SP

Bit 7 → Bit 8........Bit 15 0 * * *

SXT dst

* The status bit is affected

– The status bit is not affected

0 The status bit is cleared

1 The status bit is set

All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), the

immediate mode (#N), the absolute mode (&EDE) or the indexed mode x(RN) is used, the word that

follows contains the address information.

CPU SLAU144J–December 2004–Revised July 2013

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