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ADC12 Registers

23.3.5 ADC12IE, ADC12 Interrupt Enable Register

15 14 13 12 11 10 9 8

ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IFG9 ADC12IE8

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

7 6 5 4 3 2 1 0

ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12IE1 ADC12IE0

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

ADC12IEx Bits 15-0 Interrupt enable. These bits enable or disable the interrupt request for the ADC12IFGx bits.

0 Interrupt disabled

1 Interrupt enabled

23.3.6 ADC12IFG, ADC12 Interrupt Flag Register

15 14 13 12 11 10 9 8

ADC12IFG15 ADC12IFG14 ADC12IFG13 ADC12IFG12 ADC12IFG11 ADC12IFG10 ADC12IFG9 ADC12IFG8

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

7 6 5 4 3 2 1 0

ADC12IFG7 ADC12IFG6 ADC12IFG5 ADC12IFG4 ADC12IFG3 ADC12IFG2 ADC12IFG1 ADC12IFG0

rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)

ADC12IFGx Bits 15-0 ADC12MEMx Interrupt flag. These bits are set when corresponding ADC12MEMx is loaded with a

conversion result. The ADC12IFGx bits are reset if the corresponding ADC12MEMx is accessed, or may be

reset with software.

0 No interrupt pending

1 Interrupt pending

579

SLAU144J–December 2004–Revised July 2013 ADC12

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