Datasheet

ADC12 Registers www.ti.com
23.3.3 ADC12MEMx, ADC12 Conversion Memory Registers
15 14 13 12 11 10 9 8
0 0 0 0 Conversion Results
r0 r0 r0 r0 rw rw rw rw
7 6 5 4 3 2 1 0
Conversion Results
rw rw rw rw rw rw rw rw
Conversion Bits 15-0 The 12-bit conversion results are right-justified. Bit 11 is the MSB. Bits 15-12 are always 0. Writing to the
Results conversion memory registers corrupts the results.
23.3.4 ADC12MCTLx, ADC12 Conversion Memory Control Registers
7 6 5 4 3 2 1 0
EOS SREFx INCHx
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Can be modified only when ENC = 0
EOS Bit 7 End of sequence. Indicates the last conversion in a sequence.
0 Not end of sequence
1 End of sequence
SREFx Bits 6-4 Select reference
000 V
R+
= AV
CC
and V
R-
= AV
SS
001 V
R+
= V
REF+
and V
R-
= AV
SS
010 V
R+
= V
eREF+
and V
R-
= AV
SS
011 V
R+
= V
eREF+
and V
R-
= AV
SS
100 V
R+
= AV
CC
and V
R-
= V
REF-
/ V
eREF-
101 V
R+
= V
REF+
and V
R-
= V
REF-
/ V
eREF-
110 V
R+
= V
eREF+
and V
R-
= V
REF-
/ V
eREF-
111 V
R+
= V
eREF+
and V
R-
= V
REF-
/ V
eREF-
INCHx Bits 3-0 Input channel select
0000 A0
0001 A1
0010 A2
0011 A3
0100 A4
0101 A5
0110 A6
0111 A7
1000 V
eREF+
1001 V
REF-
/V
eREF-
1010 Temperature diode
1011 (AV
CC
- AV
SS
) / 2
1100 GND
1101 GND
1110 GND
1111 GND
578
ADC12 SLAU144J–December 2004–Revised July 2013
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