Datasheet

www.ti.com ADC12 Registers
23.3.2 ADC12CTL1, ADC12 Control Register 1
15 14 13 12 11 10 9 8
CSTARTADDx SHSx SHP ISSH
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
7 6 5 4 3 2 1 0
ADC12DIVx ADC12SSELx CONSEQx ADC12BUSY
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Can be modified only when ENC = 0
CSTARTADDx Bits 15-12 Conversion start address. These bits select which ADC12 conversion-memory register is used for a single
conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding
to ADC12MEM0 to ADC12MEM15.
SHSx Bits 11-10 Sample-and-hold source select
00 ADC12SC bit
01 Timer_A.OUT1
10 Timer_B.OUT0
11 Timer_B.OUT1
SHP Bit 9 Sample-and-hold pulse-mode select. This bit selects the source of the sampling signal (SAMPCON) to be
either the output of the sampling timer or the sample-input signal directly.
0 SAMPCON signal is sourced from the sample-input signal.
1 SAMPCON signal is sourced from the sampling timer.
ISSH Bit 8 Invert signal sample-and-hold
0 The sample-input signal is not inverted.
1 The sample-input signal is inverted.
ADC12DIVx Bits 7-5 ADC12 clock divider
000 /1
001 /2
010 /3
011 /4
100 /5
101 /6
110 /7
111 /8
ADC12SSELx Bits 4-3 ADC12 clock source select
00 ADC12OSC
01 ACLK
10 MCLK
11 SMCLK
CONSEQx Bits 2-1 Conversion sequence mode select
00 Single-channel, single-conversion
01 Sequence-of-channels
10 Repeat-single-channel
11 Repeat-sequence-of-channels
ADC12BUSY Bit 0 ADC12 busy. This bit indicates an active sample or conversion operation.
0 No operation is active.
1 A sequence, sample, or conversion is active.
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SLAU144J–December 2004–Revised July 2013 ADC12
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