Datasheet

www.ti.com ADC12 Registers
23.3.1 ADC12CTL0, ADC12 Control Register 0
15 14 13 12 11 10 9 8
SHT1x SHT0x
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
7 6 5 4 3 2 1 0
MSC REF2_5V REFON ADC120N ADC12OVIE ADC12TOVIE ENC ADC12SC
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Can be modified only when ENC = 0
SHT1x Bits 15-12 Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for
registers ADC12MEM8 to ADC12MEM15.
0000 4 ADC12CLK cycles
0001 8 ADC12CLK cycles
0010 16 ADC12CLK cycles
0011 32 ADC12CLK cycles
0100 64 ADC12CLK cycles
0101 96 ADC12CLK cycles
0110 128 ADC12CLK cycles
0111 192 ADC12CLK cycles
1000 256 ADC12CLK cycles
1001 384 ADC12CLK cycles
1010 512 ADC12CLK cycles
1011 768 ADC12CLK cycles
1100 1024 ADC12CLK cycles
1101 1024 ADC12CLK cycles
1110 1024 ADC12CLK cycles
1111 1024 ADC12CLK cycles
SHT0x Bits 11-8 Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for
registers ADC12MEM0 to ADC12MEM7.
0000 4 ADC12CLK cycles
0001 8 ADC12CLK cycles
0010 16 ADC12CLK cycles
0011 32 ADC12CLK cycles
0100 64 ADC12CLK cycles
0101 96 ADC12CLK cycles
0110 128 ADC12CLK cycles
0111 192 ADC12CLK cycles
1000 256 ADC12CLK cycles
1001 384 ADC12CLK cycles
1010 512 ADC12CLK cycles
1011 768 ADC12CLK cycles
1100 1024 ADC12CLK cycles
1101 1024 ADC12CLK cycles
1110 1024 ADC12CLK cycles
1111 1024 ADC12CLK cycles
MSC Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.
0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion.
1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-
conversions are performed automatically as soon as the prior conversion is completed.
REF2_5V Bit 6 Reference generator voltage. REFON must also be set.
0 1.5 V
1 2.5 V
575
SLAU144J–December 2004–Revised July 2013 ADC12
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