Datasheet

www.ti.com

Instruction Set

3.4.1 Double-Operand (Format I) Instructions

Figure 3-9 illustrates the double-operand instruction format.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code S-Reg Ad B/W As D-Reg

Figure 3-9. Double Operand Instruction Format

Table 3-11 lists and describes the double operand instructions.

Table 3-11. Double Operand Instructions

Status Bits

S-Reg,

Mnemonic Operation

D-Reg

V N Z C

src → dst - - - -

MOV(.B) src,dst

src + dst → dst * * * *

ADD(.B) src,dst

src + dst + C → dst * * * *

ADDC(.B) src,dst

dst + .not.src + 1 → dst * * * *

SUB(.B) src,dst

dst + .not.src + C → dst * * * *

SUBC(.B) src,dst

dst - src * * * *

CMP(.B) src,dst

src + dst + C → dst (decimally) * * * *

DADD(.B) src,dst

src .and. dst 0 * * *

BIT(.B) src,dst

not.src .and. dst → dst - - - -

BIC(.B) src,dst

src .or. dst → dst - - - -

BIS(.B) src,dst

src .xor. dst → dst * * * *

XOR(.B) src,dst

src .and. dst → dst 0 * * *

AND(.B) src,dst

* The status bit is affected

– The status bit is not affected

0 The status bit is cleared

1 The status bit is set

NOTE: Instructions CMP and SUB

The instructions CMP and SUB are identical except for the storage of the result. The same is

true for the BIT and AND instructions.

SLAU144J–December 2004–Revised July 2013 CPU

Submit Documentation Feedback