Datasheet

R
S
R
I
V
S
V
C
MSP430
C
I
V
I
V
I
= Input voltage at pin Ax
V
S
= External source voltage
R
S
= External source resistance
R
I
= Internal MUX-on input resistance
C
I
= Input capacitance
V
C
= Capacitance-charging voltage
www.ti.com ADC12 Operation
23.2.4.3 Sample Timing Considerations
When SAMPCON = 0, all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can
be modeled as an RC low-pass filter during the sampling time t
sample
, as shown in Figure 23-5. An internal
MUX-on input resistance R
I
(maximum of 2 kΩ) in series with capacitor C
I
(maximum of 40 pF) is seen by
the source. The capacitor C
I
voltage (V
C
) must be charged to within 1/2 LSB of the source voltage (V
S
) for
an accurate 12-bit conversion.
Figure 23-5. Analog Input Equivalent Circuit
The resistance of the source R
S
and R
I
affect t
sample
. The following equation can be used to calculate the
minimum sampling time t
sample
for a 12-bit conversion:
t
sample
> (R
S
+ R
I
) × ln(2
13
) × C
I
+ 800 ns
Substituting the values for R
I
and C
I
given above, the equation becomes:
t
sample
> (R
S
+ 2 kΩ) × 9.011 × 40 pF + 800 ns
For example, if R
S
is 10 kΩ, t
sample
must be greater than 5.13 µs.
23.2.5 Conversion Memory
There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx
is configured with an associated ADC12MCTLx control register. The SREFx bits define the voltage
reference and the INCHx bits select the input channel. The EOS bit defines the end of sequence when a
sequential conversion mode is used. A sequence rolls over from ADC12MEM15 to ADC12MEM0 when
the EOS bit in ADC12MCTL15 is not set.
The CSTARTADDx bits define the first ADC12MCTLx used for any conversion. If the conversion mode is
single-channel or repeat-single-channel the CSTARTADDx points to the single ADC12MCTLx to be used.
If the conversion mode selected is either sequence-of-channels or repeat-sequence-of-channels,
CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence. A pointer, not visible to
software, is incremented automatically to the next ADC12MCTLx in a sequence when each conversion
completes. The sequence continues until an EOS bit in ADC12MCTLx is processed; this is the last control
byte processed.
When conversion results are written to a selected ADC12MEMx, the corresponding flag in the ADC12IFGx
register is set.
23.2.6 ADC12 Conversion Modes
The ADC12 has four operating modes selected by the CONSEQx bits as shown in Table 23-1.
Table 23-1. Conversion Mode Summary
CONSEQx Mode Operation
00 Single channel single-conversion A single channel is converted once.
01 Sequence-of-channels A sequence of channels is converted once.
10 Repeat-single-channel A single channel is converted repeatedly.
11 Repeat-sequence-of-channels A sequence of channels is converted repeatedly.
565
SLAU144J–December 2004–Revised July 2013 ADC12
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