Datasheet

www.ti.com ADC12 Operation
23.2.2.1 Analog Port Selection
The ADC12 inputs are multiplexed with the port P6 pins, which are digital CMOS gates. When analog
signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic
current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer
eliminates the parasitic current flow and, therefore, reduces overall current consumption. The P6SELx bits
provide the ability to disable the port pin input and output buffers.
; P6.0 and P6.1 configured for analog input
BIS.B #3h,&P6SEL ; P6.1 and P6.0 ADC12 function
23.2.3 Voltage Reference Generator
The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and
2.5 V. Either of these reference voltages may be used internally and externally on pin V
REF+
.
Setting REFON = 1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V.
When REF2_5V = 0, the reference is 1.5 V. The reference can be turned off to save power when not in
use.
For proper operation, the internal voltage reference generator must be supplied with storage capacitance
across V
REF+
and AV
SS
. The recommended storage capacitance is a parallel combination of 10-µF and 0.1-
µF capacitors
.
From turn-on, a maximum of 17 ms must be allowed for the voltage reference generator to
bias the recommended storage capacitors. If the internal reference generator is not used for the
conversion, the storage capacitors are not required.
NOTE: Reference Decoupling
Approximately 200 µA is required from any reference used by the ADC12 while the two LSBs
are being resolved during a conversion. A parallel combination of 10-µF and 0.1-µF
capacitors is recommended for any reference as shown in Figure 23-11.
External references may be supplied for V
R+
and V
R-
through pins V
eREF+
and V
REF-
/V
eREF-
respectively.
23.2.4 Sample and Conversion Timing
An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source
for SHI is selected with the SHSx bits and includes the following:
• The ADC12SC bit
• The Timer_A Output Unit 1
• The Timer_B Output Unit 0
• The Timer_B Output Unit 1
The polarity of the SHI signal source can be inverted with the ISSH bit. The SAMPCON signal controls the
sample period and start of conversion. When SAMPCON is high, sampling is active. The high-to-low
SAMPCON transition starts the analog-to-digital conversion, which requires 13 ADC12CLK cycles. Two
different sample-timing methods are defined by control bit SHP, extended sample mode and pulse mode.
563
SLAU144J–December 2004–Revised July 2013 ADC12
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