Datasheet

R ~ 100 Ohm
ESD Protection
ADC12MCTLx.0−3
Input
Ax
IN R-
ADC
R+ R-
V - V
N = 4095 ×
V - V
ADC12 Operation www.ti.com
23.2 ADC12 Operation
The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed
in the following sections.
23.2.1 12-Bit ADC Core
The ADC core converts an analog input to its 12-bit digital representation and stores the result in
conversion memory. The core uses two programmable/selectable voltage levels (V
R+
and V
R-
) to define the
upper and lower limits of the conversion. The digital output (N
ADC
) is full scale (0FFFh) when the input
signal is equal to or higher than V
R+
, and the digital output is zero when the input signal is equal to or
lower than V
R-
. The input channel and the reference voltage levels (V
R+
and V
R-
) are defined in the
conversion-control memory. The conversion formula for the ADC result N
ADC
is:
The ADC12 core is configured by two control registers, ADC12CTL0 and ADC12CTL1. The core is
enabled with the ADC12ON bit. The ADC12 can be turned off when not in use to save power. With few
exceptions, the ADC12 control bits can only be modified when ENC = 0. ENC must be set to 1 before any
conversion can take place.
23.2.1.1 Conversion Clock Selection
The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse
sampling mode is selected. The ADC12 source clock is selected using the ADC12SSELx bits and can be
divided from 1 through 8 using the ADC12DIVx bits. Possible ADC12CLK sources are SMCLK, MCLK,
ACLK, and an internal oscillator ADC12OSC.
The ADC12OSC is generated internally and is in the 5-MHz range, but the frequency varies with individual
devices, supply voltage, and temperature. See the device-specific data sheet for the ADC12OSC
specification.
The application must ensure that the clock chosen for ADC12CLK remains active until the end of a
conversion. If the clock is removed during a conversion, the operation does not complete and any result is
invalid.
23.2.2 ADC12 Inputs and Multiplexer
The eight external and four internal analog signals are selected as the channel for conversion by the
analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise
injection that can result from channel switching (see Figure 23-2). The input multiplexer is also a T-switch
to minimize the coupling between channels. Channels that are not selected are isolated from the A/D, and
the intermediate node is connected to analog ground (AV
SS
) so that the stray capacitance is grounded to
help eliminate crosstalk.
The ADC12 uses the charge redistribution method. When the inputs are internally switched, the switching
action may cause transients on the input signal. These transients decay and settle before causing errant
conversion.
Figure 23-2. Analog Multiplexer
562
ADC12 SLAU144J–December 2004–Revised July 2013
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