Datasheet

www.ti.com ADC10 Registers
22.3.6 ADC10MEM, Conversion-Memory Register, 2s Complement Format
15 14 13 12 11 10 9 8
Conversion Results
r r r r r r r r
7 6 5 4 3 2 1 0
Conversion Results 0 0 0 0 0 0
r r r0 r0 r0 r0 r0 r0
Conversion Bits 15-0 The 10-bit conversion results are left-justified, 2s complement format. Bit 15 is the MSB. Bits 5-0 are always
Results 0.
22.3.7 ADC10DTC0, Data Transfer Control Register 0
7 6 5 4 3 2 1 0
Reserved ADC10TB ADC10CT ADC10B1 ADC10FETCH
r0 r0 r0 r0 rw-(0) rw-(0) r-(0) rw-(0)
Reserved Bits 7-4 Reserved. Always read as 0.
ADC10TB Bit 3 ADC10 two-block mode
0 One-block transfer mode
1 Two-block transfer mode
ADC10CT Bit 2 ADC10 continuous transfer
0 Data transfer stops when one block (one-block mode) or two blocks (two-block mode) have
completed.
1 Data is transferred continuously. DTC operation is stopped only if ADC10CT cleared, or ADC10SA
is written to.
ADC10B1 Bit 1 ADC10 block one. This bit indicates for two-block mode which block is filled with ADC10 conversion results.
ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation. ADC10TB must
also be set.
0 Block 2 is filled
1 Block 1 is filled
ADC10FETCH Bit 0 This bit should normally be reset.
22.3.8 ADC10DTC1, Data Transfer Control Register 1
7 6 5 4 3 2 1 0
DTC Transfers
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
DTC Transfers Bits 7-0 DTC transfers. These bits define the number of transfers in each block.
0 DTC is disabled
01h-0FFh Number of transfers per block
557
SLAU144J–December 2004–Revised July 2013 ADC10
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