Datasheet

www.ti.com ADC10 Registers
22.3.2 ADC10CTL1, ADC10 Control Register 1
15 14 13 12 11 10 9 8
INCHx SHSx ADC10DF ISSH
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
7 6 5 4 3 2 1 0
ADC10DIVx ADC10SSELx CONSEQx ADC10BUSY
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r-0
Can be modified only when ENC = 0
INCHx Bits 15-12 Input channel select. These bits select the channel for a single-conversion or the highest channel for a
sequence of conversions. Only available ADC channels should be selected. See device specific data sheet.
0000 A0
0001 A1
0010 A2
0011 A3
0100 A4
0101 A5
0110 A6
0111 A7
1000 V
eREF+
1001 V
REF-
/V
eREF-
1010 Temperature sensor
1011 (V
CC
- V
SS
) / 2
1100 (V
CC
- V
SS
) / 2, A12 on MSP430F22xx devices
1101 (V
CC
- V
SS
) / 2, A13 on MSP430F22xx devices
1110 (V
CC
- V
SS
) / 2, A14 on MSP430F22xx devices
1111 (V
CC
- V
SS
) / 2, A15 on MSP430F22xx devices
SHSx Bits 11-10 Sample-and-hold source select.
00 ADC10SC bit
01 Timer_A.OUT1
(1)
10 Timer_A.OUT0
(1)
11 Timer_A.OUT2 (Timer_A.OUT1 on MSP430F20x0, MSP430G2x31, and MSP430G2x30 devices)
(1)
ADC10DF Bit 9 ADC10 data format
0 Straight binary
1 2s complement
ISSH Bit 8 Invert signal sample-and-hold
0 The sample-input signal is not inverted.
1 The sample-input signal is inverted.
ADC10DIVx Bits 7-5 ADC10 clock divider
000 /1
001 /2
010 /3
011 /4
100 /5
101 /6
110 /7
111 /8
ADC10SSELx Bits 4-3 ADC10 clock source select
00 ADC10OSC
01 ACLK
10 MCLK
11 SMCLK
(1)
Timer triggers are from Timer0_Ax if more than one timer module exists on the device.
555
SLAU144J–December 2004–Revised July 2013 ADC10
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