Datasheet

ADC10 Registers www.ti.com
ADC10IFG Bit 2 ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion result. It is automatically reset
when the interrupt request is accepted, or it may be reset by software. When using the DTC this flag is set
when a block of transfers is completed.
0 No interrupt pending
1 Interrupt pending
ENC Bit 1 Enable conversion
0 ADC10 disabled
1 ADC10 enabled
ADC10SC Bit 0 Start conversion. Software-controlled sample-and-conversion start. ADC10SC and ENC may be set together
with one instruction. ADC10SC is reset automatically.
0 No sample-and-conversion start
1 Start sample-and-conversion
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ADC10 SLAU144J–December 2004–Revised July 2013
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