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ADC10 Registers
22.3.1 ADC10CTL0, ADC10 Control Register 0
15 14 13 12 11 10 9 8
SREFx ADC10SHTx ADC10SR REFOUT REFBURST
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
7 6 5 4 3 2 1 0
MSC REF2_5V REFON ADC10ON ADC10IE ADC10IFG ENC ADC10SC
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Can be modified only when ENC = 0
SREFx Bits 15-13 Select reference.
000 V
R+
= V
CC
and V
R-
= V
SS
001 V
R+
= V
REF+
and V
R-
= V
SS
010 V
R+
= V
eREF+
and V
R-
= V
SS
. Devices with V
eREF+
only.
011 V
R+
= Buffered V
eREF+
and V
R-
= V
SS
. Devices with V
eREF+
pin only.
100 V
R+
= V
CC
and V
R-
= V
REF-
/ V
eREF-
. Devices with V
eREF-
pin only.
101 V
R+
= V
REF+
and V
R-
= V
REF-
/ V
eREF-
. Devices with V
eREF+/-
pins only.
110 V
R+
= V
eREF+
and V
R-
= V
REF-
/ V
eREF-
. Devices with V
eREF+/-
pins only.
111 V
R+
= Buffered V
eREF+
and V
R-
= V
REF-
/ V
eREF-
. Devices with V
eREF+/-
pins only.
ADC10SHTx Bits 12-11 ADC10 sample-and-hold time
00 4 × ADC10CLKs
01 8 × ADC10CLKs
10 16 × ADC10CLKs
11 64 × ADC10CLKs
ADC10SR Bit 10 ADC10 sampling rate. This bit selects the reference buffer drive capability for the maximum sampling rate.
Setting ADC10SR reduces the current consumption of the reference buffer.
0 Reference buffer supports up to ~200 ksps
1 Reference buffer supports up to ~50 ksps
REFOUT Bit 9 Reference output
0 Reference output off
1 Reference output on. Devices with V
eREF+
/ V
REF+
pin only.
REFBURST Bit 8 Reference burst.
0 Reference buffer on continuously
1 Reference buffer on only during sample-and-conversion
MSC Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.
0 The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion.
1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-
conversions are performed automatically as soon as the prior conversion is completed
REF2_5V Bit 6 Reference-generator voltage. REFON must also be set.
0 1.5 V
1 2.5 V
REFON Bit 5 Reference generator on
0 Reference off
1 Reference on
ADC10ON Bit 4 ADC10 on
0 ADC10 off
1 ADC10 on
ADC10IE Bit 3 ADC10 interrupt enable
0 Interrupt disabled
1 Interrupt enabled
553
SLAU144J–December 2004–Revised July 2013 ADC10
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