Datasheet

DTC idle
DTC reset
ADC10B1 = 0
ADC10TB = 1
n=0 (ADC10DTC1)
Initialize
Start Address in ADC10SA
Wait untilADC10MEM
is written
Wait
for
CPU ready
Write to ADC10MEM
completed
Transfer data to
Address AD
AD = AD + 2
x = x − 1
Synchronize
with MCLK
1 x MCLK cycle
n is latched
in counter ’x’
x > 0
DTC init
Wait for write to
ADC10SA
Write to
ADC10SA
Write to ADC10SA
x = 0
Prepare
DTC
DTC
operation
Write to ADC10SA
or
n = 0
ADC10IFG=1
Toggle
ADC10B1
Write to ADC10SA
x = n
If ADC10B1 = 0
then AD = SA
ADC10B1 = 1
or
ADC10CT=1
ADC10CT = 0
and
ADC10B1 = 0
n = 0
n ≠ 0
ADC10 Operation www.ti.com
Figure 22-12. State Diagram for Data Transfer Control in Two-Block Transfer Mode
548
ADC10 SLAU144J–December 2004–Revised July 2013
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