Datasheet

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22.2.6.5 Using the MSC Bit
To configure the converter to perform successive conversions automatically and as quickly as possible, a
multiple sample and convert function is available. When MSC = 1 and CONSEQx > 0, the first rising edge
of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon
as the prior conversion is completed. Additional rising edges on SHI are ignored until the sequence is
completed in the single-sequence mode or until the ENC bit is toggled in repeat-single-channel, or
repeated-sequence modes. The function of the ENC bit is unchanged when using the MSC bit.
22.2.6.6 Stopping Conversions
Stopping ADC10 activity depends on the mode of operation. The recommended ways to stop an active
conversion or conversion sequence are:
• Resetting ENC in single-channel single-conversion mode stops a conversion immediately and the
results are unpredictable. For correct results, poll the ADC10BUSY bit until reset before clearing ENC.
• Resetting ENC during repeat-single-channel operation stops the converter at the end of the current
conversion.
• Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the
sequence.
• Any conversion mode may be stopped immediately by setting the CONSEQx = 0 and resetting the
ENC bit. Conversion data is unreliable.
22.2.7 ADC10 Data Transfer Controller
The ADC10 includes a data transfer controller (DTC) to automatically transfer conversion results from
ADC10MEM to other on-chip memory locations. The DTC is enabled by setting the ADC10DTC1 register
to a nonzero value.
When the DTC is enabled, each time the ADC10 completes a conversion and loads the result to
ADC10MEM, a data transfer is triggered. No software intervention is required to manage the ADC10 until
the predefined amount of conversion data has been transferred. Each DTC transfer requires one CPU
MCLK. To avoid any bus contention during the DTC transfer, the CPU is halted, if active, for the one
MCLK required for the transfer.
A DTC transfer must not be initiated while the ADC10 is busy. Software must ensure that no active
conversion or sequence is in progress when the DTC is configured:
; ADC10 activity test
BIC.W #ENC,&ADC10CTL0 ;
busy_test BIT.W #BUSY,&ADC10CTL1 ;
JNZ busy_test ;
MOV.W #xxx,&ADC10SA ; Safe
MOV.B #xx,&ADC10DTC1 ;
; continue setup
544
ADC10 SLAU144J–December 2004–Revised July 2013
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