Datasheet
R
S
R
I
V
S
V
C
MSP430
C
I
V
I
V
I
= Input voltage at pin Ax
V
S
= External source voltage
R
S
= External source resistance
R
I
= Internal MUX-on input resistance
C
I
= Input capacitance
V
C
= Capacitance-charging voltage
Start
Sampling
Stop
Sampling
Conversion
Complete
SAMPCON
SHI
t
sample
t
convert
t
sync
13 x ADC10CLKs
Start
Conversion
ADC10CLK
ADC10 Operation
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22.2.5 Sample and Conversion Timing
An analog-to-digital conversion is initiated with a rising edge of sample input signal SHI. The source for
SHI is selected with the SHSx bits and includes the following:
• The ADC10SC bit
• The Timer_A Output Unit 1
• The Timer_A Output Unit 0
• The Timer_A Output Unit 2
The polarity of the SHI signal source can be inverted with the ISSH bit. The SHTx bits select the sample
period t
sample
to be 4, 8, 16, or 64 ADC10CLK cycles. The sampling timer sets SAMPCON high for the
selected sample period after synchronization with ADC10CLK.Total sampling time is t
sample
plus t
sync
.The
high-to-low SAMPCON transition starts the analog-to-digital conversion, which requires 13 ADC10CLK
cycles as shown in Figure 22-3.
Figure 22-3. Sample Timing
22.2.5.1 Sample Timing Considerations
When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can
be modeled as an RC low-pass filter during the sampling time t
sample
, as shown in Figure 22-4. An internal
MUX-on input resistance R
I
(2 kΩ maximum) in series with capacitor C
I
(27 pF maximum) is seen by the
source. The capacitor C
I
voltage V
C
must be charged to within ½ LSB of the source voltage V
S
for an
accurate 10-bit conversion.
Figure 22-4. Analog Input Equivalent Circuit
The resistance of the source R
S
and R
I
affect t
sample
.The following equations can be used to calculate the
minimum sampling time for a 10-bit conversion.
t
sample
> (R
S
+ R
I
) × ln(2
11
) × C
I
Substituting the values for R
I
and C
I
given above, the equation becomes:
t
sample
> (R
S
+ 2 kΩ) × 7.625 × 27 pF
538
ADC10 SLAU144J–December 2004–Revised July 2013
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