Datasheet

R ~ 100Ohm
ESD Protection
INCHx
Input
Ax
IN R–
ADC
R+ R–
V – V
N = 1023 ×
V – V
ADC10 Operation www.ti.com
22.2 ADC10 Operation
The ADC10 module is configured with user software. The setup and operation of the ADC10 is discussed
in the following sections.
22.2.1 10-Bit ADC Core
The ADC core converts an analog input to its 10-bit digital representation and stores the result in the
ADC10MEM register. The core uses two programmable/selectable voltage levels (V
R+
and V
R-
) to define
the upper and lower limits of the conversion. The digital output (N
ADC
) is full scale (03FFh) when the input
signal is equal to or higher than V
R+
, and zero when the input signal is equal to or lower than V
R-
. The input
channel and the reference voltage levels (V
R+
and V
R-
) are defined in the conversion-control memory.
Conversion results may be in straight binary format or 2s-complement format. The conversion formula for
the ADC result when using straight binary format is:
The ADC10 core is configured by two control registers, ADC10CTL0 and ADC10CTL1. The core is
enabled with the ADC10ON bit. With few exceptions the ADC10 control bits can only be modified when
ENC = 0. ENC must be set to 1 before any conversion can take place.
22.2.1.1 Conversion Clock Selection
The ADC10CLK is used both as the conversion clock and to generate the sampling period. The ADC10
source clock is selected using the ADC10SSELx bits and can be divided from 1 to 8 using the
ADC10DIVx bits. Possible ADC10CLK sources are SMCLK, MCLK, ACLK, and internal oscillator
ADC10OSC .
The ADC10OSC, generated internally, is in the 5-MHz range, but varies with individual devices, supply
voltage, and temperature. See the device-specific data sheet for the ADC10OSC specification.
The user must ensure that the clock chosen for ADC10CLK remains active until the end of a conversion. If
the clock is removed during a conversion, the operation does not complete, and any result is invalid.
22.2.2 ADC10 Inputs and Multiplexer
The eight external and four internal analog signals are selected as the channel for conversion by the
analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise
injection that can result from channel switching (see Figure 22-2). The input multiplexer is also a T-switch
to minimize the coupling between channels. Channels that are not selected are isolated from the A/D, and
the intermediate node is connected to analog ground (V
SS
) so that the stray capacitance is grounded to
help eliminate crosstalk.
The ADC10 uses the charge redistribution method. When the inputs are internally switched, the switching
action may cause transients on the input signal. These transients decay and settle before causing errant
conversion.
Figure 22-2. Analog Multiplexer
536
ADC10 SLAU144J–December 2004–Revised July 2013
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