Datasheet

Sample
and
Hold
10−bitSAR
Divider
/1 ../8
AV
CC
ACLK
MCLK
SMCLK
ADC10SC
TA1
TA0
Data Transfer
Controller
RAM, Flash, Peripherials
V
R−
V
R+
Ve
REF+
V
REF+
ADC10ON
INCHx
REFBURST
ADC10SSELx
ADC10DIVx
SHSx
ADC10SHTx
MSC
ENC
BUSY
ADC10DF
ADC10CLK
SREF2
ADC10TB ADC10B1ADC10CT
ISSH
ADC10SR
ADC10OSC
Ref_x
S/H Convert
SAMPCON
1
0
Sync
Sample Timer
/4/8/16/64
SHI
ADC10SA
n
4
A0
A1
A2
A3
A4
A5
A6
A7
REFON
INCHx=0Ah
2_5V
1.5Vor 2.5V
Reference
on
Ref_x
SREF1
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
000111
01
SREF0
10
CONSEQx
AV
SS
1
0
INCHx=0Bh
Auto
ADC10MEM
R
R
0
1
REFOUT
SREF1
1001
1000
0010
0001
0011
0100
0101
0110
0111
0000
1011
1010
0001
1111
1110
1101
1100
A12
†
A13
†
A14
†
A15
†
† MSP430F22xxdevicesonly.Channels A12-A15areavailablein Channels A12-A15tiedtochannel A11inotherdevices.Not
allchannelsareavailableinalldevices.
‡TA1onMSP430F20x2,MSP430G2x31,andMSP430G2x30devices
V
REF−
/V
eREF−
AV
CC
AV
SS
AV
CC
TA2
‡
†
†
†
†
†
†
†
†
www.ti.com ADC10 Introduction
Figure 22-1. ADC10 Block Diagram
535
SLAU144J–December 2004–Revised July 2013 ADC10
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated