Datasheet

Comparator_A+ Registers www.ti.com
21.3.2 CACTL2, Comparator_A+, Control Register
7 6 5 4 3 2 1 0
CASHORT P2CA4 P2CA3 P2CA2 P2CA1 P2CA0 CAF CAOUT
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r-(0)
CASHORT Bit 7 Input short. This bit shorts the + and - input terminals.
0 Inputs not shorted
1 Inputs shorted
P2CA4 Bit 6 Input select. This bit together with P2CA0 selects the + terminal input when CAEX = 0 and the - terminal
input when CAEX = 1.
P2CA3
(1)
Bits 5-3 Input select. These bits select the - terminal input when CAEX = 0 and the + terminal input when CAEX = 1.
P2CA2
000 No connection
P2CA1
001 CA1
010 CA2
011 CA3
100 CA4
101 CA5
110 CA6
111 CA7
P2CA0 Bit 2 Input select. This bit, together with P2CA4, selects the + terminal input when CAEX = 0 and the - terminal
input when CAEX = 1.
00 No connection
01 CA0
10 CA1
11 CA2
CAF Bit 1 Comparator_A+ output filter
0 Comparator_A+ output is not filtered
1 Comparator_A+ output is filtered
CAOUT Bit 0 Comparator_A+ output. This bit reflects the value of the comparator output. Writing this bit has no effect.
(1)
MSP430G2210: Only channels 2, 5, 6, and 7 are available. Other channels should not be selected.
21.3.3 CAPD, Comparator_A+, Port Disable Register
7 6 5 4 3 2 1 0
CAPD7 CAPD6 CAPD5 CAPD4 CAPD3 CAPD2 CAPD1 CAPD0
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
CAPDx
(1)
Bits 7-0 Comparator_A+ port disable. These bits individually disable the input buffer for the pins of the port
associated with Comparator_A+. For example, if CA0 is on pin P2.3, the CAPDx bits can be used to
individually enable or disable each P2.x pin buffer. CAPD0 disables P2.0, CAPD1 disables P2.1, etc.
0 The input buffer is enabled.
1 The input buffer is disabled.
(1)
MSP430G2210: Channels 2, 5, 6, and 7 are available. Other channels should not be disabled.
532
Comparator_A+ SLAU144J–December 2004–Revised July 2013
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