Datasheet

www.ti.com USART Registers: SPI Mode
19.3.8 UxTXBUF, USART Transmit Buffer Register
7 6 5 4 3 2 1 0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
rw rw rw rw rw rw rw rw
UxTXBUFx Bits 7-0 The transmit data buffer is user accessible and contains current data to be transmitted. When seven-bit
character-length is used, the data should be MSB justified before being moved into UxTXBUF. Data is
transmitted MSB first. Writing to UxTXBUF clears UTXIFGx.
19.3.9 ME1, Module Enable Register 1
7 6 5 4 3 2 1 0
USPIE0
rw-0
Bit 7 This bit may be used by other modules. See device-specific data sheet.
USPIE0 Bit 6 USART0 SPI enable. This bit enables the SPI mode for USART0.
0 Module not enabled
1 Module enabled
Bits 5-0 These bits may be used by other modules. See device-specific data sheet.
19.3.10 ME2, Module Enable Register 2
7 6 5 4 3 2 1 0
USPIE1
rw-0
Bits 7-5 These bits may be used by other modules. See device-specific data sheet.
USPIE1 Bit 4 USART1 SPI enable. This bit enables the SPI mode for USART1.
0 Module not enabled
1 Module enabled
Bits 3-0 These bits may be used by other modules. See device-specific data sheet.
19.3.11 IE1, Interrupt Enable Register 1
7 6 5 4 3 2 1 0
UTXIE0 URXIE0
rw-0 rw-0
UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.
0 Interrupt not enabled
1 Interrupt enabled
URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt.
0 Interrupt not enabled
1 Interrupt enabled
Bits 5-0 These bits may be used by other modules. See device-specific data sheet.
509
SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, SPI Mode
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