Datasheet

USART Registers: SPI Mode www.ti.com
19.3.3 UxRCTL, USART Receive Control Register
7 6 5 4 3 2 1 0
FE Unused OE Unused
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
FE Bit 7 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode.
0 No conflict detected
1 A negative edge occurred on STE, indicating bus conflict
Unused Bit 6 Unused
OE Bit 5 Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous
character was read. OE is automatically reset when UxRXBUF is read, when SWRST = 1, or can be reset
by software.
0 No error
1 Overrun error occurred
Unused Bits 4-0 Unused
19.3.4 UxBR0, USART Baud Rate Control Register 0
7 6 5 4 3 2 1 0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
rw rw rw rw rw rw rw rw
19.3.5 UxBR1, USART Baud Rate Control Register 1
7 6 5 4 3 2 1 0
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
rw rw rw rw rw rw rw rw
UxBRx The baud-rate generator uses the content of {UxBR1+UxBR0} to set the baud rate. Unpredictable SPI
operation occurs if UxBR < 2.
19.3.6 UxMCTL, USART Modulation Control Register
7 6 5 4 3 2 1 0
m7 m6 m5 m4 m3 m2 m1 m0
rw rw rw rw rw rw rw rw
UxMCTLx Bits 7-0 The modulation control register is not used for SPI mode and should be set to 000h.
19.3.7 UxRXBUF, USART Receive Buffer Register
7 6 5 4 3 2 1 0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
r r r r r r r r
UxRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift
register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB
justified and the MSB is always reset.
508
USART Peripheral Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated