Datasheet

www.ti.com USART Registers: SPI Mode
19.3.1 UxCTL, USART Control Register
7 6 5 4 3 2 1 0
Unused I2C CHAR LISTEN SYNC MM SWRST
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1
Unused Bits 7-6 Unused
I2C Bit 5 I
2
C mode enable. This bit selects I
2
C or SPI operation when SYNC = 1.
0 SPI mode
1 I
2
C mode
CHAR Bit 4 Character length
0 7-bit data
1 8-bit data
LISTEN Bit 3 Listen enable. The LISTEN bit selects the loopback mode
0 Disabled
1 Enabled. The transmit signal is internally fed back to the receiver.
SYNC Bit 2 Synchronous mode enable
0 UART mode
1 SPI mode
MM Bit 1 Master mode
0 USART is slave
1 USART is master
SWRST Bit 0 Software reset enable
0 Disabled. USART reset released for operation.
1 Enabled. USART logic held in reset state.
19.3.2 UxTCTL, USART Transmit Control Register
7 6 5 4 3 2 1 0
CKPH CKPL SSELx Unused STC TXEPT
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1
CKPH Bit 7 Clock phase select.
0 Data is changed on the first UCLK edge and captured on the following edge.
1 Data is captured on the first UCLK edge and changed on the following edge.
CKPL Bit 6 Clock polarity select
0 The inactive state is low.
1 The inactive state is high.
SSELx Bits 5-4 Source select. These bits select the BRCLK source clock.
00 External UCLK (valid for slave mode only)
01 ACLK (valid for master mode only)
10 SMCLK (valid for master mode only)
11 SMCLK (valid for master mode only)
Unused Bits 3-2 Unused
STC Bit 1 Slave transmit control.
0 4-pin SPI mode: STE enabled.
1 3-pin SPI mode: STE disabled.
TXEPT Bit 0 Transmitter empty flag. The TXEPT flag is not used in slave mode.
0 Transmission active and/or data waiting in UxTXBUF
1 UxTXBUF and TX shift register are empty
507
SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, SPI Mode
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