Datasheet

CKPH CKPL
Cycle#
UCLK
UCLK
UCLK
UCLK
SIMO/
SOMI
SIMO/
SOMI
Move to UxTXBUF
RX Sample Points
0
1
0
0
01
1 1
0 X
1 X
MSB
MSB
1 2 3 4 5 6 7 8
LSB
LSB
TX Data Shifted Out
STE
BRCLK
Baud rate = with UxBR= [UxBR1, UxBR0]
UxBR
Bit Start
mX
BRCLK
88
UCLKI
ACLK
SMCLK
SMCLK 11
BITCLK
10
01
00
2
0
2
7
2
8
2
15
Compare (0 or 1)
Modulation Data Shift Register
(LSB first)
16−Bit Counter
Q0
............
Q15
m0m7
...
...
8
UxBR1 UxBR0
Toggle
FF
N =
R
R
R
UxMCTL
SSEL1 SSEL0
www.ti.com USART Operation: SPI Mode
Figure 19-8. SPI Baud Rate Generator
The 16-bit value of UxBR0+UxBR1 is the division factor of the USART clock source, BRCLK. The
maximum baud rate that can be generated in master mode is BRCLK/2. The maximum baud rate that can
be generated in slave mode is BRCLK The modulator in the USART baud rate generator is not used for
SPI mode and is recommended to be set to 000h. The UCLK frequency is given by:
19.2.5.1 Serial Clock Polarity and Phase
The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the
USART. Timing for each case is shown in Figure 19-9.
Figure 19-9. USART SPI Timing
503
SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, SPI Mode
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