Datasheet

Idle State
(Receive
Enabled)
Receive
Disable
Receiver
Collects
Character
USPIEx = 0
No Clock at UCLK
Not Completed
USPIEx = 1
USPIEx = 0
USPIEx = 1
Handle Interrupt
Conditions
Character
Received
USPIEx = 1
USPIEx = 0
SWRST
PUC
External Clock
Present
Idle State
(Receiver
Enabled)
Receive
Disable
Receiver
Collects
Character
USPIEx = 0
No Data Written
to UxTXBUF
Not Completed
USPIEx = 1
USPIEx = 0
USPIEx = 1
Handle Interrupt
Conditions
Character
Received
USPIEx = 1
USPIEx = 0
SWRST
PUC
Data Written
to UxTXBUF
Idle State
(Transmitter
Enabled)
Transmit
Disable
Transmission
Active
USPIEx = 0
No Clock at UCLK
Not Completed
USPIEx = 1
USPIEx = 0
USPIEx = 1
Handle Interrupt
Conditions
Character
Transmitted
USPIEx = 1
USPIEx = 0
SWRST
PUC
External Clock
Present
USART Operation: SPI Mode www.ti.com
Figure 19-5. Slave Transmit Enable State Diagram
19.2.4.2 Receive Enable
The SPI receive enable state diagrams are shown in Figure 19-6 and Figure 19-7. When USPIEx = 0,
UCLK is disabled from shifting data into the RX shift register.
Figure 19-6. SPI Master Receive-Enable State Diagram
Figure 19-7. SPI Slave Receive-Enable State Diagram
19.2.5 Serial Clock Control
UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud
rate generator on the UCLK pin as shown in Figure 19-8. When MM = 0, the USART clock is provided on
the UCLK pin by the master and, the baud rate generator is not used and the SSELx bits are “don’t care”.
The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer.
502
USART Peripheral Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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