Datasheet

Idle State
(Transmitter
Enabled)
Transmit
Disable
Transmission
Active
USPIEx = 0
No Data Written
to Transfer Buffer
Not Completed
USPIEx = 1
USPIEx = 0
USPIEx = 1,
Data Written to
Transmit Buffer
Handle Interrupt
Conditions
Character
Transmitted
USPIEx = 1
USPIEx = 0 And Last Buffer
Entry Is Transmitted
SWRST
PUC
USPIEx = 0
Receive Buffer UxRXBUF
Receive Shift Register
LSB
MSB
Transmit Buffer UxTXBUF
Transmit Shift Register
LSB
MSB
SPI Receive Buffer
Data Shift Register DSR
LSB
MSB
SOMISOMI
SIMOSIMO
MASTER SLAVE
Px.x STE
STE
SS
Port.x
UCLK
SCLK
MSP430 USARTCOMMON SPI
www.ti.com USART Operation: SPI Mode
Figure 19-3. USART Slave and External Master
19.2.3.1 Four-Pin SPI Slave Mode
In 4-pin slave mode, STE is used by the slave to enable the transmit and receive operations and is
provided by the SPI master. When STE is low, the slave operates normally. When STE is high:
• Any receive operation in progress on SIMO is halted
• SOMI is set to the input direction
A high STE signal does not reset the USART module. The STE input signal is not used in 3-pin slave
mode.
19.2.4 SPI Enable
The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx
= 0, the USART stops operation after the current transfer completes, or immediately if no operation is
active. A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated.
19.2.4.1 Transmit Enable
When USPIEx = 0, any further write to UxTXBUF does not transmit. Data written to UxTXBUF begin to
transmit when USPIEx = 1 and the BRCLK source is active. Figure 19-4 and Figure 19-5 show the
transmit enable state diagrams.
Figure 19-4. Master Transmit Enable State Diagram
501
SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, SPI Mode
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