Datasheet

Receive Buffer UxRXBUF
Receive Shift Register
MSB
LSB
Transmit Buffer UxTXBUF
Transmit Shift Register
MSB
LSB
SPI Receive Buffer
Data Shift Register (DSR)
MSB
LSB
SOMI SOMI
SIMO SIMO
MASTER SLAVE
Px.x STE
STE
SS
Port.x
UCLK
SCLK
MSP430 USART COMMON SPI
USART Operation: SPI Mode www.ti.com
19.2.2 Master Mode
Figure 19-2 shows the USART as a master in both 3-pin and 4-pin configurations. The USART initiates a
data transfer when data is moved to the transmit data buffer UxTXBUF. The UxTXBUF data is moved to
the TX shift register when the TX shift register is empty, initiating data transfer on SIMO starting with the
most significant bit. Data on SOMI is shifted into the receive shift register on the opposite clock edge,
starting with the most significant bit. When the character is received, the receive data is moved from the
RX shift register to the received data buffer UxRXBUF and the receive interrupt flag, URXIFGx, is set,
indicating the RX/TX operation is complete.
Figure 19-2. USART Master and External Slave
A set transmit interrupt flag, UTXIFGx, indicates that data has moved from UxTXBUF to the TX shift
register and UxTXBUF is ready for new data. It does not indicate RX/TX completion. In master mode, the
completion of an active transmission is indicated by a set transmitter empty bit TXEPT = 1.
To receive data into the USART in master mode, data must be written to UxTXBUF because receive and
transmit operations operate concurrently.
19.2.2.1 Four-Pin SPI Master Mode
In 4-pin master mode, STE is used to prevent conflicts with another master. The master operates normally
when STE is high. When STE is low:
• SIMO and UCLK are set to inputs and no longer drive the bus
• The error bit FE is set indicating a communication integrity violation to be handled by the user
A low STE signal does not reset the USART module. The STE input signal is not used in 3-pin master
mode.
19.2.3 Slave Mode
Figure 19-3 shows the USART as a slave in both 3-pin and 4-pin configurations. UCLK is used as the
input for the SPI clock and must be supplied by the external master. The data transfer rate is determined
by this clock and not by the internal baud rate generator. Data written to UxTXBUF and moved to the TX
shift register before the start of UCLK is transmitted on SOMI. Data on SIMO is shifted into the receive
shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are
received. When data is moved from the RX shift register to UxRXBUF, the URXIFGx interrupt flag is set,
indicating that data has been received. The overrun error bit, OE, is set when the previously received data
is not read from UxRXBUF before new data is moved to UxRXBUF.
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USART Peripheral Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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