Datasheet

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9.2.2 SVS Comparator Operation ................................................................................... 337
9.2.3 Changing the VLDx Bits ........................................................................................ 337
9.2.4 SVS Operating Range .......................................................................................... 338
9.3 SVS Registers ............................................................................................................ 339
9.3.1 SVSCTL, SVS Control Register ............................................................................... 340
10 Watchdog Timer+ (WDT+) ................................................................................................. 341
10.1 Watchdog Timer+ (WDT+) Introduction ............................................................................... 342
10.2 Watchdog Timer+ Operation ........................................................................................... 344
10.2.1 Watchdog Timer+ Counter .................................................................................... 344
10.2.2 Watchdog Mode ................................................................................................ 344
10.2.3 Interval Timer Mode ........................................................................................... 344
10.2.4 Watchdog Timer+ Interrupts .................................................................................. 344
10.2.5 Watchdog Timer+ Clock Fail-Safe Operation .............................................................. 345
10.2.6 Operation in Low-Power Modes ............................................................................. 345
10.2.7 Software Examples ............................................................................................ 345
10.3 Watchdog Timer+ Registers ............................................................................................ 346
10.3.1 WDTCTL, Watchdog Timer+ Register ...................................................................... 347
10.3.2 IE1, Interrupt Enable Register 1 ............................................................................. 348
10.3.3 IFG1, Interrupt Flag Register 1 ............................................................................... 348
11 Hardware Multiplier .......................................................................................................... 349
11.1 Hardware Multiplier Introduction ....................................................................................... 350
11.2 Hardware Multiplier Operation .......................................................................................... 350
11.2.1 Operand Registers ............................................................................................. 351
11.2.2 Result Registers ................................................................................................ 351
11.2.3 Software Examples ............................................................................................ 352
11.2.4 Indirect Addressing of RESLO ............................................................................... 353
11.2.5 Using Interrupts ................................................................................................ 353
11.3 Hardware Multiplier Registers .......................................................................................... 354
12 Timer_A .......................................................................................................................... 355
12.1 Timer_A Introduction .................................................................................................... 356
12.2 Timer_A Operation ....................................................................................................... 357
12.2.1 16-Bit Timer Counter .......................................................................................... 357
12.2.2 Starting the Timer .............................................................................................. 358
12.2.3 Timer Mode Control ........................................................................................... 358
12.2.4 Capture/Compare Blocks ..................................................................................... 362
12.2.5 Output Unit ...................................................................................................... 363
12.2.6 Timer_A Interrupts ............................................................................................. 367
12.3 Timer_A Registers ....................................................................................................... 369
12.3.1 TACTL, Timer_A Control Register ........................................................................... 370
12.3.2 TAR, Timer_A Register ....................................................................................... 371
12.3.3 TACCRx, Timer_A Capture/Compare Register x .......................................................... 371
12.3.4 TACCTLx, Capture/Compare Control Register ............................................................ 372
12.3.5 TAIV, Timer_A Interrupt Vector Register ................................................................... 373
13 Timer_B .......................................................................................................................... 374
13.1 Timer_B Introduction .................................................................................................... 375
13.1.1 Similarities and Differences From Timer_A ................................................................ 375
13.2 Timer_B Operation ....................................................................................................... 377
13.2.1 16-Bit Timer Counter .......................................................................................... 377
13.2.2 Starting the Timer .............................................................................................. 377
13.2.3 Timer Mode Control ........................................................................................... 377
13.2.4 Capture/Compare Blocks ..................................................................................... 381
13.2.5 Output Unit ...................................................................................................... 384
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SLAU144J–December 2004–Revised July 2013 Contents
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