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USART Operation: SPI Mode

19.2 USART Operation: SPI Mode

In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by

the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is

controlled by the master.

Three or four signals are used for SPI data exchange:

• SIMO: Slave in, master out

– Master mode: SIMO is the data output line.

– Slave mode: SIMO is the data input line.

• SOMI: Slave out, master in

– Master mode: SOMI is the data input line.

– Slave mode: SOMI is the data output line.

• UCLK: USART SPI clock

– Master mode: UCLK is an output.

– Slave mode: UCLK is an input.

• STE: Slave transmit enable. Used in 4-pin mode to allow multiple masters on a single bus. Not used in

3-pin mode.

– 4-pin master mode:

• When STE is high, SIMO and UCLK operate normally.

• When STE is low, SIMO and UCLK are set to the input direction.

– 4-pin slave mode:

• When STE is high, RX/TX operation of the slave is disabled and SOMI is forced to the input

direction.

• When STE is low, RX/TX operation of the slave is enabled and SOMI operates normally.

19.2.1 USART Initialization and Reset

The USART is reset by a PUC or by the SWRST bit. After a PUC, the SWRST bit is automatically set,

keeping the USART in a reset condition. When set, the SWRST bit resets the URXIEx, UTXIEx,

URXIFGx, OE, and FE bits and sets the UTXIFGx flag. The USPIEx bit is not altered by SWRST. Clearing

SWRST releases the USART for operation.

NOTE: Initializing or Reconfiguring the USART Module

The required USART initialization/reconfiguration process is:

1. Set SWRST (BIS.B #SWRST,&UxCTL)

2. Initialize all USART registers with SWRST=1 (including UxCTL)

3. Enable USART module via the MEx SFRs (USPIEx)

4. Clear SWRST via software (BIC.B #SWRST,&UxCTL)

5. Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx)

Failure to follow this process may result in unpredictable USART behavior.

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SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, SPI Mode

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