Datasheet

Receiver Shift Register
Transmit Shift Register
Receiver Buffer UxRXBUF
Transmit Buffer UxTXBUF
LISTEN MM
UCLK
Clock Phase and Polarity
Receive Status
SYNC CKPH CKPL
SSEL1 SSEL0
UCLKI
ACLK
SMCLK
SMCLK
00
01
10
11
OEPE BRK
TXWAKE
UCLKS
UCLKI
Receive Control
RXERR
FE
SWRST USPIEx* URXEIE
URXWIE
Transmit Control
SWRST USPIEx* TXEPT
RXWAKE
SPB CHAR PENAPEV
SPB CHAR PENAPEV
WUT
SIMO
UTXD
URXD
SOMI
STE
Prescaler/Divider UxBRx
Modulator UxMCTL
Baud−Rate Generator
UTXIFGx*
* See the device-specific data sheet for SFR locations.
SYNC
URXIFGx*
01
0
0
0
1
0
1
1
1
0
1
STC
SYNC= 1
USART Introduction: SPI Mode www.ti.com
19.1 USART Introduction: SPI Mode
In synchronous mode, the USART connects the MSP430 to an external system via three or four pins:
SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared.
SPI mode features include:
• 7-bit or 8-bit data length
• 3-pin and 4-pin SPI operation
• Master or slave modes
• Independent transmit and receive shift registers
• Separate transmit and receive buffer registers
• Selectable UCLK polarity and phase control
• Programmable UCLK frequency in master mode
• Independent interrupt capability for receive and transmit
Figure 19-1 shows the USART when configured for SPI mode.
Figure 19-1. USART Block Diagram: SPI Mode
498
USART Peripheral Interface, SPI Mode SLAU144J–December 2004–Revised July 2013
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