Datasheet

www.ti.com USART Registers: UART Mode
18.3.9 IE1, Interrupt Enable Register 1
7 6 5 4 3 2 1 0
UTXIE0 URXIE0
rw-0 rw-0
UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.
0 Interrupt not enabled
1 Interrupt enabled
URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt.
0 Interrupt not enabled
1 Interrupt enabled
Bits 5-0 These bits may be used by other modules. See device-specific data sheet.
18.3.10 IE2, Interrupt Enable Register 2
7 6 5 4 3 2 1 0
UTXIE1 URXIE1
rw-0 rw-0
Bits 7-6 These bits may be used by other modules. See device-specific data sheet.
UTXIE1 Bit 5 USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt.
0 Interrupt not enabled
1 Interrupt enabled
URXIE1 Bit 4 USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt.
0 Interrupt not enabled
1 Interrupt enabled
Bits 3-0 These bits may be used by other modules. See device-specific data sheet.
18.3.11 IFG1, Interrupt Flag Register 1
7 6 5 4 3 2 1 0
UTXIFG0 URXIFG0
rw-1 rw-0
UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.
0 No interrupt pending
1 Interrupt pending
URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character.
0 No interrupt pending
1 Interrupt pending
Bits 5-0 These bits may be used by other modules. See device-specific data sheet.
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SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, UART Mode
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