Datasheet

USART Registers: UART Mode www.ti.com
18.3.6 UxMCTL, USART Modulation Control Register
7 6 5 4 3 2 1 0
m7 m6 m5 m4 m3 m2 m1 m0
rw rw rw rw rw rw rw rw
UxMCTLx Modulation bits. These bits select the modulation for BRCLK.
18.3.7 UxRXBUF, USART Receive Buffer Register
7 6 5 4 3 2 1 0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
r r r r r r r r
UxRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift
register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data
mode, UxRXBUF is LSB justified and the MSB is always reset.
18.3.8 UxTXBUF, USART Transmit Buffer Register
7 6 5 4 3 2 1 0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
rw rw rw rw rw rw rw rw
UxTXBUFx Bits 7-0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift
register and transmitted on UTXDx. Writing to the transmit data buffer clears UTXIFGx. The MSB of
UxTXBUF is not used for 7-bit data and is reset.
494
USART Peripheral Interface, UART Mode SLAU144J–December 2004–Revised July 2013
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