Datasheet

www.ti.com USART Registers: UART Mode
18.3.3 UxRCTL, USART Receive Control Register
7 6 5 4 3 2 1 0
FE PE OE BRK URXEIE URXWIE RXWAKE RXERR
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
FE Bit 7 Framing error flag
0 No error
1 Character received with low stop bit
PE Bit 6 Parity error flag. When PENA = 0, PE is read as 0.
0 No error
1 Character received with parity error
OE Bit 5 Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous
character was read.
0 No error
1 Overrun error occurred
BRK Bit 4 Break detect flag
0 No break condition
1 Break condition occurred
URXEIE Bit 3 Receive erroneous-character interrupt-enable
0 Erroneous characters rejected and URXIFGx is not set
1 Erroneous characters received set URXIFGx
URXWIE Bit 2 Receive wake-up interrupt-enable. This bit enables URXIFGx to be set when an address character is
received. When URXEIE = 0, an address character does not set URXIFGx if it is received with errors.
0 All received characters set URXIFGx
1 Only received address characters set URXIFGx
RXWAKE Bit 1 Receive wake-up flag
0 Received character is data
1 Received character is an address
RXERR Bit 0 Receive error flag. This bit indicates a character was received with error(s). When RXERR = 1, on or more
error flags (FE, PE, OE, BRK) is also set. RXERR is cleared when UxRXBUF is read.
0 No receive errors detected
1 Receive error detected
18.3.4 UxBR0, USART Baud Rate Control Register 0
7 6 5 4 3 2 1 0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
rw rw rw rw rw rw rw rw
18.3.5 UxBR1, USART Baud Rate Control Register 1
7 6 5 4 3 2 1 0
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
rw rw rw rw rw rw rw rw
UxBRx The valid baud-rate control range is 3 ≤ UxBR ≤ 0FFFFh, where UxBR = (UxBR1 + UxBR0). Unpredictable
receive and transmit timing occurs if UxBR < 3.
493
SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, UART Mode
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