Datasheet

USART Registers: UART Mode

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18.3.2 UxTCTL, USART Transmit Control Register

7 6 5 4 3 2 1 0

Unused CKPL SSELx URXSE TXWAKE Unused TXEPT

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1

Unused Bit 7 Unused

CKPL Bit 6 Clock polarity select

0 UCLKI = UCLK

1 UCLKI = inverted UCLK

SSELx Bits 5-4 Source select. These bits select the BRCLK source clock.

00 UCLKI

01 ACLK

10 SMCLK

11 SMCLK

URXSE Bit 3 UART receive start-edge. The bit enables the UART receive start-edge feature.

0 Disabled

1 Enabled

TXWAKE Bit 2 Transmitter wake

0 Next frame transmitted is data

1 Next frame transmitted is an address

Unused Bit 1 Unused

TXEPT Bit 0 Transmitter empty flag

0 UART is transmitting data and/or data is waiting in UxTXBUF

1 Transmitter shift register and UxTXBUF are empty or SWRST = 1

492

USART Peripheral Interface, UART Mode SLAU144J–December 2004–Revised July 2013

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