Datasheet

j
i
i=1
baud rate UxBR
Error [%] = × 2 × m0 + int + i × UxBR + m – 1 – j × 100%
BRCLK 2
ì ü
æ ö
é ù
é ù
ï ï
æ ö
ç ÷
ê ú
í ý
ê ú
ç ÷
ç ÷
ê ú
è ø
ë û
ï ï
ç ÷
ê ú
ë û
è ø
î þ
å
1 2 3 4 5 6
0
i
t
0
t
ideal
7 8
1
t
1
2
9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7
t
0
t
1
t
2
ST D0 D1
D0 D1
ST
Synchronization Error ± 0.5x BRCLK
Int(UxBR/2)+m0 =
Int (13/2)+1 = 6+1 = 7
Majority Vote Taken Majority Vote Taken
UxBR +m1 = 13+1 = 14 UxBR +m2 = 13+0 = 13
Majority Vote Taken
BRCLK
URXDx
URXDS
t
actual
Sample
URXDS
www.ti.com USART Operation: UART Mode
18.2.6.4 Receive Bit Timing
Receive timing is subject to two error sources. The first is the bit-to-bit timing error. The second is the
error between a start edge occurring and the start edge being accepted by the USART. Figure 18-9 shows
the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock.
Figure 18-9. Receive Error
The ideal start bit timing t
ideal(0)
is half the baud-rate timing t
baudrate
, because the bit is tested in the middle of
its period. The ideal baud-rate timing t
ideal(i)
for the remaining character bits is the baud rate timing t
baudrate
.
The individual bit errors can be calculated by:
Where,
baud rate = the required baud rate
BRCLK = the input frequency; selected for UCLK, ACLK, or SMCLK
j = 0 for the start bit, 1 for data bit D0, and so on
UxBR = the division factor in registers UxBR1 and UxBR0
For example, the receive errors for the following conditions are calculated:
Baud rate = 2400
BRCLK = 32 768 Hz (ACLK)
UxBR = 13, since the ideal division factor is 13.65
UxMCTL = 6B: m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1. The LSB of
UxMCTL is used first.
485
SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, UART Mode
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