Datasheet

n–1
i
i=0
BRCLK BRCLK
Baud rate = +
N
1
UxBR + m
n
å
n–1
i
i=0
1
N = UxBR + m
n
å
BRCLK
N =
Baud Rate
N/2
Bit Start
BRCLK
Counter
BITCLK
N/2−1 N/2−2
1 N/2 N/2−1 1 N/2 N/2−1
N/2−2
0 N/2 N/2−11
INT(N/2) + m(= 0)
INT(N/2) + m(= 1)
1 0 N/2
Bit Period
N
EVEN
: INT(N/2)
N
ODD
: INT(N/2) + R(= 1)
m: corresponding modulation bit
R: Remainder from N/2 division
Majority Vote:
(m= 0)
(m= 1)
USART Operation: UART Mode www.ti.com
Figure 18-8. BITCLK Baud Rate Timing
18.2.6.1 Baud Rate Bit Timing
The first stage of the baud rate generator is the 16-bit counter and comparator. At the beginning of each
bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the
combination of UxBR0 and UxBR1. The counter reloads INT(N/2) for each bit period half-cycle, giving a
total bit period of N BRCLKs. For a given BRCLK clock source, the baud rate used determines the
required division factor N:
The division factor N is often a non-integer value of which the integer portion can be realized by the
prescaler/divider. The second stage of the baud rate generator, the modulator, is used to meet the
fractional part as closely as possible. The factor N is then defined as:
Where,
N = Target division factor
UxBR = 16-bit representation of registers UxBR0 and UxBR1
i = Bit position in the character
n = Total number of bits in the character
m
i
= Data of each corresponding modulation bit (1 or 0)
The BITCLK can be adjusted from bit to bit with the modulator to meet timing requirements when a non-
integer divisor is needed. Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit m
i
is set. Each time a bit is received or transmitted, the next bit in the modulation control register determines
the timing for that bit. A set modulation bit increases the division factor by one while a cleared modulation
bit maintains the division factor given by UxBR.
The timing for the start bit is determined by UxBR plus m0, the next bit is determined by UxBR plus m1,
and so on. The modulation sequence begins with the LSB. When the character is greater than 8 bits, the
modulation sequence restarts with m0 and continues until all bits are processed.
482
USART Peripheral Interface, UART Mode SLAU144J–December 2004–Revised July 2013
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