Datasheet

ST Address SP ST Data SP ST Data SP
Blocks of
Characters
Idle Periods of No Significance
UTXDx/URXDx
Expanded
UTXDx/URXDx
First Character Within Block
Is an Address. AD Bit Is 1
AD Bit Is 0 for
Data Within Block.
Idle Time Is of No Significance
UTXDx/URXDx
1 0 0
www.ti.com USART Operation: UART Mode
The URXWIE bit is used to control data reception in the address-bit multiprocessor format. If URXWIE is
set, data characters (address bit = 0) are assembled by the receiver but are not transferred to UxRXBUF
and no interrupts are generated. When a character containing a set address bit is received, the receiver is
temporarily activated to transfer the character to UxRXBUF and set URXIFGx. All applicable error status
flags are also set.
If an address is received, user software must reset URXWIE to continue receiving data. If URXWIE
remains set, only address characters (address bit = 1) are received. The URXWIE bit is not modified by
the USART hardware automatically.
Figure 18-4. Address-Bit Multiprocessor Format
For address transmission in address-bit multiprocessor mode, the address bit of a character can be
controlled by writing to the TXWAKE bit. The value of the TXWAKE bit is loaded into the address bit of the
character transferred from UxTXBUF to the transmit shift register, automatically clearing the TXWAKE bit.
TXWAKE must not be cleared by software. It is cleared by USART hardware after it is transferred to WUT
or by setting SWRST.
18.2.3.3 Automatic Error Detection
Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter
than the deglitch time t
τ
(approximately 300 ns) is ignored. See the device-specific data sheet for
parameters.
When a low period on URXDx exceeds t
τ
a majority vote is taken for the start bit. If the majority vote fails
to detect a valid start bit the USART halts character reception and waits for the next low period on
URXDx. The majority vote is also used for each bit in a character to prevent bit errors.
The USART module automatically detects framing errors, parity errors, overrun errors, and break
conditions when receiving characters. The bits FE, PE, OE, and BRK are set when their respective
condition is detected. When any of these error flags are set, RXERR is also set. The error conditions are
described in Table 18-1.
479
SLAU144J–December 2004–Revised July 2013 USART Peripheral Interface, UART Mode
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