Datasheet

USCI Registers: I
2
C Mode www.ti.com
17.4.11 IE2, Interrupt Enable Register 2
7 6 5 4 3 2 1 0
UCB0TXIE UCB0RXIE
rw-0 rw-0
Bits 7-4 These bits may be used by other modules (see the device-specific data sheet).
UCB0TXIE Bit 3 USCI_B0 transmit interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCB0RXIE Bit 2 USCI_B0 receive interrupt enable
0 Interrupt disabled
1 Interrupt enabled
Bits 1-0 These bits may be used by other modules (see the device-specific data sheet).
17.4.12 IFG2, Interrupt Flag Register 2
7 6 5 4 3 2 1 0
UCB0TXIFG UCB0RXIFG
rw-1 rw-0
Bits 7-4 These bits may be used by other modules (see the device-specific data sheet).
UCB0TXIFG Bit 3 USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty.
0 No interrupt pending
1 Interrupt pending
UCB0RXIFG Bit 2 USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character.
0 No interrupt pending
1 Interrupt pending
Bits 1-0 These bits may be used by other modules (see the device-specific data sheet).
17.4.13 UC1IE, USCI_B1 Interrupt Enable Register
7 6 5 4 3 2 1 0
Unused UCB1TXIE UCB1RXIE
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
Unused Bits 7-4 Unused
UCB1TXIE Bit 3 USCI_B1 transmit interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCB1RXIE Bit 2 USCI_B1 receive interrupt enable
0 Interrupt disabled
1 Interrupt enabled
Bits 1-0 These bits may be used by other USCI modules (see the device-specific data sheet).
472
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
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