Datasheet

www.ti.com USCI Registers: I
2
C Mode
17.4.8 UCBxI2COA, USCIBx I
2
C Own Address Register
15 14 13 12 11 10 9 8
UCGCEN 0 0 0 0 0 I2COAx
rw-0 r0 r0 r0 r0 r0 rw-0 rw-0
7 6 5 4 3 2 1 0
I2COAx
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
UCGCEN Bit 15 General call response enable
0 Do not respond to a general call
1 Respond to a general call
I2COAx Bits 9-0 I
2
C own address. The I2COAx bits contain the local address of the USCI_Bx I
2
C controller. The address is
right-justified. In 7-bit addressing mode, bit 6 is the MSB, and bits 9-7 are ignored. In 10-bit addressing
mode, bit 9 is the MSB.
17.4.9 UCBxI2CSA, USCI_Bx I
2
C Slave Address Register
15 14 13 12 11 10 9 8
0 0 0 0 0 0 I2CSAx
r0 r0 r0 r0 r0 r0 rw-0 rw-0
7 6 5 4 3 2 1 0
I2CSAx
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
I2CSAx Bits 9-0 I
2
C slave address. The I2CSAx bits contain the slave address of the external device to be addressed by the
USCI_Bx module. It is only used in master mode. The address is right-justified. In 7-bit slave addressing
mode, bit 6 is the MSB, and bits 9-7 are ignored. In 10-bit slave addressing mode, bit 9 is the MSB.
17.4.10 UCBxI2CIE, USCI_Bx I
2
C Interrupt Enable Register
7 6 5 4 3 2 1 0
Reserved UCNACKIE UCSTPIE UCSTTIE UCALIE
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
Reserved Bits 7-4 Reserved
UCNACKIE Bit 3 Not-acknowledge interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCSTPIE Bit 2 Stop condition interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCSTTIE Bit 1 Start condition interrupt enable
0 Interrupt disabled
1 Interrupt enabled
UCALIE Bit 0 Arbitration lost interrupt enable
0 Interrupt disabled
1 Interrupt enabled
471
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
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