Datasheet

USCI Registers: I
2
C Mode www.ti.com
17.4.5 UCBxSTAT, USCI_Bx Status Register
7 6 5 4 3 2 1 0
Unused UCSCLLOW UCGC UCBBUSY UCNACKIFG UCSTPIFG UCSTTIFG UCALIFG
rw-0 r-0 rw-0 r-0 rw-0 rw-0 rw-0 rw-0
Unused Bit 7 Unused.
UCSCLLOW Bit 6 SCL low
0 SCL is not held low
1 SCL is held low
UCGC Bit 5 General call address received. UCGC is automatically cleared when a START condition is received.
0 No general call address received
1 General call address received
UCBBUSY Bit 4 Bus busy
0 Bus inactive
1 Bus busy
UCNACKIFG Bit 3 Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is
received.
0 No interrupt pending
1 Interrupt pending
UCSTPIFG Bit 2 Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received.
0 No interrupt pending
1 Interrupt pending
UCSTTIFG Bit 1 Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received.
0 No interrupt pending
1 Interrupt pending
UCALIFG Bit 0 Arbitration lost interrupt flag
0 No interrupt pending
1 Interrupt pending
17.4.6 UCBxRXBUF, USCI_Bx Receive Buffer Register
7 6 5 4 3 2 1 0
UCRXBUFx
r r r r r r r r
UCRXBUFx Bits 7-0 The receive-data buffer is user accessible and contains the last received character from the receive shift
register. Reading UCBxRXBUF resets UCBxRXIFG.
17.4.7 UCBxTXBUF, USCI_Bx Transmit Buffer Register
7 6 5 4 3 2 1 0
UCTXBUFx
rw rw rw rw rw rw rw rw
UCTXBUFx Bits 7-0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift
register and transmitted. Writing to the transmit data buffer clears UCBxTXIFG.
470
SLAU144J–December 2004–Revised July 2013
Universal Serial Communication Interface, I
2
C Mode
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated